Printed circuit boards (“PCBs”) populated with silicon chips typically require termination resistors for terminating the transmission lines that run throughout the PCBs. Termination resistors are necessary for good signal integrity at a high frequency operation.
Termination resistors can be integrated within the silicon chips or placed directly on the PCB. Traditionally, the termination resistors are placed on the PCB board because of the difficulties in designing high quality resistors in a silicon chip. However, as electronic systems on PCBs become more and more complicated, there is a large number of input receivers/output drivers that need termination, and consequently it has becomes very difficult to place all of the termination resistors on PCB board. Therefore, the need for the termination resistors to be placed on silicon chips, as on-die termination (“ODT”) resistors, has increased.
To compensate for the resistance change caused by process and temperature variations, digital compensation circuits have been used to make sure an ODT resistance is within a pre-determined range over different process corners (i.e., statistical variation process parameters) and temperature. Difficulties arise, however, because the device parameters in these circuits greatly vary with process and temperature conditions, and because the I-V characteristics of MOS transistors used in these circuits are non-linear.
To improve the linearity of an ODT resistor, a number of structures have been explored, including an all-PMOS active resistor structure disclosed in J. Griffin et al., “Large Signal Active Resistor Output Drive”, IEEE 42nd Symposium on Circuits and Systems (Aug. 8–11, 1999), hereinafter “Griffin”. FIG. 1 is a circuit diagram of the active ODT resistor 10 disclosed in Griffin. ODT resistor 10 includes positive-channel metal-oxide semiconductor (“PMOS”) transistors 12–14. With resistor 10, the size (i.e., the channel width/channel length ratio) of transistors 12 and 13 are the same, but the size of transistor 14 must be approximately four times the size of transistors 12 and 13 to achieve linearity.
The all-PMOS ODT resistor shown in FIG. 1 has good linearity when used in digital compensation circuits where the gate bias VGG of transistor 12 at terminal 17 is set to VSS. In this case, transistor 12 is in the linear region until the pad terminal voltage (or output voltage Vo) 16 is lower than its PMOS threshold voltage Vt.
However, the use of digital impedance control include the disadvantages of step-like impedance adjustments (normally 5˜10%), switching noise generation from turning on/off the different legs of the ODT resistor, interference with data transmission, and the need for a state machine in order to update resistor value.
In analog impedance control, the compensation is accomplished by changing the gate bias. However, the linearity of transistor 12 of FIG. 1 deteriorates when VGG reaches approximately Vcc/2 at fast process corner and lower temperature. This is because transistor 12 enters the saturation region when the pad voltage is lower than Vcc/2+Vt.
Based on the foregoing, there is a need for an improved ODT resistor suitable for analog impedance control, and an analog feedback loop that provides a suitable gate bias for the ODT resistor.